A typical digital phase locked loop (DPLL) consists of a phase detector to detect a phase of a reference signal and a feedback signal, a digitally controlled oscillator (DCO) to generate an output clock signal, a digital loop filter to generate fine and/or coarse control code to control the frequency of the output clock signal from DCO, and a divider to divide the output clock signal from the DCO to generate the feedback signal. During normal operation of the DPLL, the digital filter generates a coarse control code for the DCO and freezes that coarse control code. The digital filter then adjusts the fine control code to gradually change the frequency of the DCO till a phase lock is achieved by the DPLL. The term “changing the frequency of the output signal from the DCO” and “changing the frequency of the DCO” are interchangeably used.
As temperature of a processor comprising the DPLL changes, a fine control code to control the frequency of the output signal from DCO of the DPLL also changes. This change in the fine control code due to temperature change/drift may require that the DPLL be designed with a wider range of fine control code to compensate for temperature changes, power supply drifting, aging of devices of the DPLL, and other forms of process variations. Without a wider range of fine control code, the fine control code may run out of range while trying to lock the DPLL and trying to compensate for the above mentioned changes. An unlocked DPLL means that the processor may not have phase locked clock signals and so the processor may not operate properly.
However, designing a DCO to operate for a wider range of fine control code, to compensate for the changes mentioned above, results in a larger sized DCO which results in higher power consumption, larger silicon area, and higher quantization noise of the DCO. Furthermore, the logic unit for generating a wider range of fine code settings requires more logic to generate more bits for the fine control code.